--- /sys/src/9k/k10/mp.c
+++ /sys/src/9k/k10/mp.c
@@ -6,6 +6,7 @@
 
 #include "io.h"
 #include "apic.h"
+#include "mp.h"
 
 /*
  * MultiProcessor Specification Version 1.[14].
@@ -93,7 +94,7 @@ mpmkintr(u8int* p)
 		default:
 			mpintrprint("INTIN botch", p);
 			return 0;
-		case 3:				/* IOINTR */
+		case PcmpIOINTR:
 			apic = &ioapic[p[6]];
 			if(!apic->useable){
 				mpintrprint("unuseable APIC", p);
@@ -104,7 +105,7 @@ mpmkintr(u8int* p)
 				return 0;
 			}
 			break;
-		case 4:				/* LINTR */
+		case PcmpLINTR:
 			apic = &xapic[p[6]];
 			if(!apic->useable){
 				mpintrprint("unuseable APIC", p);
@@ -118,7 +119,7 @@ mpmkintr(u8int* p)
 		}
 	}
 	n = l16get(p+2);
-	if((polarity = (n & 0x03)) == 2 || (trigger = ((n>>2) & 0x03)) == 2){
+	if((polarity = (n & PcmpPOMASK)) == 2 || (trigger = ((n>>2) & PcmpPOMASK)) == 2){
 		mpintrprint("invalid polarity/trigger", p);
 		return 0;
 	}
@@ -136,15 +137,15 @@ mpmkintr(u8int* p)
 	default:
 		mpintrprint("invalid type", p);
 		return 0;
-	case 0:					/* INT */
+	case PcmpINT:
 		switch(polarity){
 		case 0:
 			v |= mpbus[p[4]]->polarity;
 			break;
-		case 1:
+		case PcmpHIGH:
 			v |= IPhigh;
 			break;
-		case 3:
+		case PcmpLOW:
 			v |= IPlow;
 			break;
 		}
@@ -152,21 +153,21 @@ mpmkintr(u8int* p)
 		case 0:
 			v |= mpbus[p[4]]->trigger;
 			break;
-		case 1:
+		case PcmpHIGH:
 			v |= TMedge;
 			break;
-		case 3:
+		case PcmpLOW:
 			v |= TMlevel;
 			break;
 		}
 		break;
-	case 1:					/* NMI */
+	case PcmpNMI:
 		v |= TMedge|IPhigh|MTnmi;
 		break;
-	case 2:					/* SMI */
+	case PcmpSMI:
 		v |= TMedge|IPhigh|MTsmi;
 		break;
-	case 3:					/* ExtINT */
+	case PcmpExtINT:
 		v |= TMedge|IPhigh|MTei;
 		break;
 	}
@@ -194,7 +195,7 @@ mpparse(PCMP* pcmp)
 		}
 		print("\n");
 		break;
-	case 0:					/* processor */
+	case PcmpPROCESSOR:
 		/*
 		 * Initialise the APIC if it is enabled (p[3] & 0x01).
 		 * p[1] is the APIC ID, the memory mapped address comes
@@ -208,7 +209,7 @@ mpparse(PCMP* pcmp)
 			apicinit(p[1], l32get(pcmp->apicpa), p[3] & 0x02);
 		p += 20;
 		break;
-	case 1:					/* bus */
+	case PcmpBUS:
 		DBG("mpparse: bus: %d type %6.6s\n", p[1], (char*)p+2);
 		if(mpbus[p[1]] != nil){
 			print("mpparse: bus %d already allocated\n", p[1]);
@@ -235,7 +236,7 @@ mpparse(PCMP* pcmp)
 
 		p += 8;
 		break;
-	case 2:					/* IOAPIC */
+	case PcmpIOAPIC:
 		/*
 		 * Initialise the IOAPIC if it is enabled (p[3] & 0x01).
 		 * p[1] is the APIC ID, p[4-7] is the memory mapped address.
@@ -247,7 +248,7 @@ mpparse(PCMP* pcmp)
 
 		p += 8;
 		break;
-	case 3:					/* IOINTR */
+	case PcmpIOINTR:
 		/*
 		 * p[1] is the interrupt type;
 		 * p[2-3] contains the polarity and trigger mode;
@@ -285,7 +286,7 @@ mpparse(PCMP* pcmp)
 
 		p += 8;
 		break;
-	case 4:					/* LINTR */
+	case PcmpLINTR:
 		/*
 		 * Format is the same as IOINTR above.
 		 */
@@ -330,19 +331,19 @@ mpparse(PCMP* pcmp)
 		}
 		print("\n");
 		break;
-	case 128:
+	case PcmpSASM:
 		DBG("address space mapping\n");
 		DBG(" bus %d type %d base %#llux length %#llux\n",
 			p[2], p[3], l64get(p+4), l64get(p+12));
 		p += p[1];
 		break;
-	case 129:
+	case PcmpHIERARCHY:
 		DBG("bus hierarchy descriptor\n");
 		DBG(" bus %d sd %d parent bus %d\n",
 			p[2], p[3], p[4]);
 		p += p[1];
 		break;
-	case 130:
+	case PcmpCBASM:
 		DBG("compatibility bus address space modifier\n");
 		DBG(" bus %d pr %d range list %d\n",
 			p[2], p[3], l32get(p+4));
--- /dev/null
+++ /sys/src/9k/k10/mp.h
@@ -0,0 +1,85 @@
+/*
+ * MultiProcessor Specification Version 1.[14].
+ */
+
+enum {					/* table entry types */
+	PcmpPROCESSOR	= 0x00,		/* one entry per processor */
+	PcmpBUS		= 0x01,		/* one entry per bus */
+	PcmpIOAPIC	= 0x02,		/* one entry per I/O APIC */
+	PcmpIOINTR	= 0x03,		/* one entry per bus interrupt source */
+	PcmpLINTR	= 0x04,		/* one entry per system interrupt source */
+
+	PcmpSASM	= 0x80,
+	PcmpHIERARCHY	= 0x81,
+	PcmpCBASM	= 0x82,
+
+					/* PCMPprocessor and PCMPioapic flags */
+	PcmpEN		= 0x01,		/* enabled */
+	PcmpBP		= 0x02,		/* bootstrap processor */
+
+					/* PCMPiointr and PCMPlintr flags */
+	PcmpPOMASK	= 0x03,		/* polarity conforms to specifications of bus */
+	PcmpHIGH	= 0x01,		/* active high */
+	PcmpLOW		= 0x03,		/* active low */
+	PcmpELMASK	= 0x0C,		/* trigger mode of APIC input signals */
+	PcmpEDGE	= 0x04,		/* edge-triggered */
+	PcmpLEVEL	= 0x0C,		/* level-triggered */
+
+					/* PCMPiointr and PCMPlintr interrupt type */
+	PcmpINT		= 0x00,		/* vectored interrupt from APIC Rdt */
+	PcmpNMI		= 0x01,		/* non-maskable interrupt */
+	PcmpSMI		= 0x02,		/* system management interrupt */
+	PcmpExtINT	= 0x03,		/* vectored interrupt from external PIC */
+
+					/* PCMPsasm addrtype */
+	PcmpIOADDR	= 0x00,		/* I/O address */
+	PcmpMADDR	= 0x01,		/* memory address */
+	PcmpPADDR	= 0x02,		/* prefetch address */
+
+					/* PCMPhierarchy info */
+	PcmpSD		= 0x01,		/* subtractive decode bus */
+
+					/* PCMPcbasm modifier */
+	PcmpPR		= 0x01,		/* predefined range list */
+};
+
+enum {
+	MaxAPICNO	= 254,		/* 255 is physical broadcast */
+};
+
+enum {					/* I/O APIC registers */
+	IoapicID	= 0x00,		/* ID */
+	IoapicVER	= 0x01,		/* version */
+	IoapicARB	= 0x02,		/* arbitration ID */
+	IoapicRDT	= 0x10,		/* redirection table */
+};
+
+/*
+ * Common bits for
+ *	I/O APIC Redirection Table Entry;
+ *	Local APIC Local Interrupt Vector Table;
+ *	Local APIC Inter-Processor Interrupt;
+ *	Local APIC Timer Vector Table.
+ */
+enum {
+	ApicFIXED	= 0x00000000,	/* [10:8] Delivery Mode */
+	ApicLOWEST	= 0x00000100,	/* Lowest priority */
+	ApicSMI		= 0x00000200,	/* System Management Interrupt */
+	ApicRR		= 0x00000300,	/* Remote Read */
+	ApicNMI		= 0x00000400,
+	ApicINIT	= 0x00000500,	/* INIT/RESET */
+	ApicSTARTUP	= 0x00000600,	/* Startup IPI */
+	ApicExtINT	= 0x00000700,
+
+	ApicPHYSICAL	= 0x00000000,	/* [11] Destination Mode (RW) */
+	ApicLOGICAL	= 0x00000800,
+
+	ApicDELIVS	= 0x00001000,	/* [12] Delivery Status (RO) */
+	ApicHIGH	= 0x00000000,	/* [13] Interrupt Input Pin Polarity (RW) */
+	ApicLOW		= 0x00002000,
+	ApicRemoteIRR	= 0x00004000,	/* [14] Remote IRR (RO) */
+	ApicEDGE	= 0x00000000,	/* [15] Trigger Mode (RW) */
+	ApicLEVEL	= 0x00008000,
+	ApicIMASK	= 0x00010000,	/* [16] Interrupt Mask */
+};
+